Non-volatile memory cells are used to store data in integrated circuits. As portable and battery powered devices become increasingly important in the consumer products industry, the need for permanent data storage when batteries lose power or between uses of a battery powered product, increases. Examples of consumer products that require non-volatile storage are battery operated devices such as cell phones, portable computers such as laptops, notebooks and PDAs, wireless email terminals, MP3 audio and video players, portable wireless web browsers and the like, and these integrated circuits increasingly include on-board data storage. As is known in the art.
A commercially important type of non-volatile storage is the NAND flash array. These arrays offer good storage density and permanent data storage, however the erase and program cycles are performed to address several cells at once. Another type of non-volatile storage is NOR Flash, which is more suitable when random access to individual cells is required, NOR flash cells are arranged with individual bit and word lines accessing individual cells, however the density of these arrays is lower and so the amount of data storage/unit area is also much lower. Both types of non-volatile memory are becoming increasingly prevalent in various applications for storage of data, voice, images, audio and video.
FIG. 1 depicts a type of non-volatile charge trapping storage cell. In FIG. 1, a semiconductor substrate region 11 is shown in a cross sectional view. Source and drain regions 15 and 25 are formed using conventional semiconductor process doping steps to dope the substrate followed by an anneal step to cause thermal diffusion to form the source and drain diffusions to the desired depth. A dielectric stack, typically oxide nitride oxide or so-called “ONO”, is formed from deposition and patterning steps as are known in the art. Oxide 23, nitride 13, and oxide 19 are deposited or grown over the substrate. Polysilicon gate 17 is formed to complete the storage cell, this gate is the control gate and will be used to receive the word line or row line voltage. This planar non-volatile cell, a single gate non-volatile device, can be programmed by adjusting the threshold voltage so that the cell is either conducting, or non-conducting, in the presence of a read voltage on the control gate. By assigning a logical value of 1 or 0 to the state of conducting, or non-conducting, the cell may be programmed to store a data value. The program state involves trapping charge at the nitride, which acts to make the cell conductive or non conductive in subsequent read cycles. This programming step is reversible so that the storage cell may be programmed for many thousands of cycles.
As one approach to forming useful densities of the non-volatile cell of FIG. 1, a stacked arrangement using silicon on insulator or SOI layers as the vertically stacked “substrate regions” could be used. FIG. 1 depicts the effect of repeated thermal processes on the planar silicon ONO silicon, or SONOS, non-volatile cell in the dashed area. For example, in a typical stacking arrangement, the first layer of cells could be formed on the silicon substrate, with subsequent layers of cells being formed on SOI layers built up vertically. To manufacture this structure, each additional source drain region annealing step performed at each layer would subject the lower, already completed cells, to additional thermal processes. In FIG. 1, the undesired additional thermal diffusion of the source and drain regions is shown, if this undesired diffusion continues over many process steps the two regions may even electrically contact and close the channel region between them, causing device failure. Even if such a failure does not occur, the source and drain diffusion changes the channel length, and affects the operation of the device after it is completed, resulting in unpredictable threshold voltages (Vt) and other deleterious effects.
A need thus exists for improved SONOS non-volatile storage cells, methods for manufacturing the cells, and circuitry and methods that substantially maintain the advantages of the SONOS non-volatile cells and the layout efficiency and compactness of the prior art cell approaches, while offering an efficient solution to the thermal diffusion problems associated with the known three dimensional cell arrays of the prior art.